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SPD EEPROM: Functioning Algorithm

With the advent of the new SDRAM standard, a new I2C interface has also appeared. The interface was developed by Philips and is used as an internal auxiliary bus of the motherboard for exchanging information with non-volatile memory SPD-EEPROM (installed on the PCB SDRAM), which is responsible for identifying the components installed on the module. The bus is characterized by extreme ease of implementation – 2 signal lines, the transmission or reception of information on which is carried out programmatically. For its intended purpose, only the motherboard BIOS applies this bus so far to determine the characteristics of SDRAM. Changes to the EEPROM during system operation are not foreseen. However, the possibility of changing information in the EEPROM (rewriting) exists and can lead to a situation where the user accidentally or purposefully tries to change his parameters. The method of program access to the bus is not standardized yet, but having a description of the chipset, it can be easily “calculated”.

DIMM configuration engine
The type and parameters of the installed DIMM module are determined through the Serial Presence Detect mechanism defined by the JEDEC 168 pin DIMM Standard. For interaction with EEPROM, special software control is not provided in the chipsets; therefore, information on the type and size of memory is obtained via the I2C serial interface. Before any interactions with memory will be provided, it is necessary to initialize the chipset registers responsible for its operation. The type and size of the SDRAM memory is determined via the SMB interface on the PIIX4E (only for Intel chipsets). The SCL and SDA EEPROM pins, which determine serial data transfer over the I2C bus, are directly connected to the SMB on the PIIX4E. Thus, the data is read from the Serial Presence Detect Port on the DIMM module through a series of sequential read cycles and fed to the South Bridge on the motherboard, where they are written to the control chipset registers. The I2C serial interface provides bidirectional data transfer between a pair of devices using two signals: SDA (Serial Data) and SCL (Serial Clock) synchronization. Two devices are involved in the exchange – the master (Master) and the slave (Slave). Each of them can act as a transmitter that places information bits on the SDA line, or a receiver that reads information from the SDA line. Synchronization is set by the master device – the controller. In the case of SDRAM, the host device is the I440 chipset. The SDA data line is bidirectional, with an open collector type output and is controlled by both devices in turn. The method of transmitting information is start-stop. The beginning of any transmission of information – the Start condition – is initiated by the translation of the SDA signal from high to low at high SCL level. Information transfer is completed by transferring the SDA signal from a low level to a high level at a high SCL level – the Stop condition. Data bits during transmission are gated by a positive SCL edge. Each piece of information consists of 8 bits of data generated by the transmitter, after which the transmitter releases the data line to receive confirmation. The receiver during the 9th cycle generates a zero confirmation bit – Ack. Each slave device has its own address, the bit capacity of which is 7 bits. The 7-bit address contains 2 parts. The high four bits A (6: 3) carry information about the type of device. For EEPROM – 1010. Explanations are needed here.

The I2C interface is designed as universal, and its use with SDRAM is a special case. Just the code 1010 in the 4 higher digits A (6: 3) determines that the type of device the controller works with is the SPD EEPROM memory.

The interface allows the controller using a pair of signals to access any of 8 devices of the same type connected to this bus and having a unique address. The lower 3 bits of A (0: 2) determine the device number in the EEPROM (see simplified block diagram).

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