But this is not Intel at all!
The ways of AMD and Intel, from our point of view, have long diverged. If earlier it was possible to install at least Intel or at least AMD into the same “motherboard”, then for some time now the owner of a board with an AMD processor cannot install an Intel processor in it and vice versa. Therefore, AMD without any hesitation switched to a new (for Intel architecture processors) EV6 system bus. The EV6 bus (from Alpha) initially runs at 200 MHz. But its specification provides for operation at a frequency of up to 400 MHz. This in itself inspires hope. But the main thing in this bus is that the system logic set is not connected to a common bus for all elements (as in GTL + Bus for the P-III processor), but is connected directly to the processor and other devices via separate lines (see Fig. 2).
I think that even without additional explanations, the potentially huge superiority of the EV6 bus over that used with the P-III processors is understandable. A particularly large advantage is expected for multiprocessor structures, which AMD promises not to ignore in the very near future. The processors will not wait for the shared bus to be freed. Each will connect to the system logic with its own separate channel. Unlike Athlon, in Intel multiprocessor systems, processors are forced to compete for a common backbone.
Thus, on the one hand (according to the command system, at least) Athlon seems to be Intel architecture, and on the other (in its structure) it seems to be gone.
Changed and some other processor elements. In particular, cache memory. The cache in AMD processors has always been surprising. How can you make such a large cache with such a low processor price? This time, too, was not without an increase in its volume. The Athlon processor has a level 1 cache of 128 kB (64 for instructions and 64 for data) and a second level cache of up to 8 MB. There is one more subtlety. The processor clock speed is easier to raise than the cache clock speed. In order not to create any difficulties for himself in the future, AMD designed the cache controller in such a way that the second-level cache can work at the core frequency, at half frequency, and even at a frequency of 1/3 of the processor core frequency. Isn’t this AMD sly?